Using CAD Tools for Shortening the Design Cycle of High- Performance Σ∆M: A 16.4bit 9.6kHz 1.71mW Σ∆M in CMOS 0.7μm Technology

This paper uses a CAD methodology proposed by the authors to design a low-power 2ndorder Σ∆M. This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy metering mixed-signal ASIC and features 16.4bit at a digital output rate of 9.6kHz with a power consumption of 1.71mW. It yields a value of the figure which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable Σ∆Ms using CAD methodologies.